this document is a general product descripti on and is subject to change without notice. hynix semiconductor inc does not assum e any responsibility for use of circuits descr ibed. no patent licenses are implied. rev.01 /oct.2002 hynix semiconductor hy62sf16804b series 512kx16bit full cmos sram document title 512k x16 bit 1.8v super low power full cmos slow sram revision history revision no history draft date remark 00 initial release may.29.2001 pre liminary 01 dc electrical characteristics oct.22.2002 final - icc changed 4ma -> 3ma - icc1 changed 25ma at 70ns -> 15ma at 70ns - icc1 changed 3ma at 1us -> 2ma at 1us - isb (ttl) changed 50ua -> 300ua ac test loads - (r1//r2) 4091ohm // 3273ohm -> 3070ohm // 3150ohm ac test conditions - output load changed 5pf -> 30pf - input pulse level 0.4v to 1.6v -> 0.2v to vcc-0.2 data retention electric characteristic - iccdr ll-part changed 20ua -> 10ua
hy62sf16804b rev.01/oct. 2002 2 description the hy62sf16804b is a high speed, super low power and 8mbit full cmos sram organized as 512k words by 16bits. the hy62sf16804b uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well-suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2v. features ? fully static operati on and tri-state output ? ttl compatible inputs and outputs ? battery backup(ll/sl-part) - 1.2v(min) data retention ? standard pin configuration - 48-fbga product voltage speed operation st andby current(ua) temperature no. (v) (ns) current/icc(ma) ll sl ( c) hy62sf16804b-c 1.65~2.3 70/85/100 3 15 8 0~70 hy62sf16804b-i 1.65~2.3 70/85/100 3 15 8 -40~85 note 1. c : commercial, i : industrial 2. current value is max. pin connection ( top view ) block diagram pin description pin name pin function pin name pin function /cs chip select i/o1~i/o16 data inputs / outputs /we write enable a0~a18 address inputs /oe output enable vcc power(1.65v~2.3v) /lb lower byte control(i/o1~i/o8) vss ground /ub upper byte control( i/o9~i/o16) nc no connection / lb io9 io10 / oe a0 a1 a2 nc / ub a3 a4 / cs io1 io11 a5 a6 io2 io3 vss io12 a17 a7 io4 vcc vcc io13 vss a16 io5 vss io15 io14 a14 a15 io6 io7 io16 nc a12 a13 / we io8 a18 a8 a9 a10 a11 nc 1 2 3 4 5 6 a b c d e f g h memory array 256k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o8 i/o9 i/o16 column decoder block decoder pre decoder add input buffer a0 a18 /cs /oe /lb /ub /we
hy62sf16804b rev.01/oct. 2002 2 ordering information part no. speed power package temp. hy62sf16804b-dfc 70/85/100 ll-part fbga c hy62sf16804b-sfc 70/85/100 sl-part fbga c hy62sf16804b-dfi 70/85/100 ll-part fbga i hy62sf16804b-sfi 70/85/100 sl-part fbga i note 1. c : commercial, i : industrial absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage -0.3 to vcc+0.3 v vcc power supply -0.3 to 2.6v v 0 to 70 c hy62sf16804b-c t a operating temperature -40 to 85 c hy62sf16804b-i t stg storage temperature -55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 ? 10 c ? sec note 1. stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is stress rating only and the f unctional operation of the device under these or any other conditions above those indicated in t he operation of this specification is not implied. exposure to the absolute maximum rating condi tions for extended period may affect reliability. truth table i/o /cs /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x deselected high-z high-z standby x x x h h deselected high-z high-z standby l h h l x output disabled high-z high-z active l h h x l output disabled high-z high-z active l h l l h read d out high-z active h l high-z d out l l d out d out l l x l h write d in high-z active h l high-z d in l l d in d in note: 1. h=v ih , l=v il , x=don't care(v ih or v il) 2. ub, lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o1 -i/o8. when ub is low, data is writt en or read to the upper byte, i/o9 -i/o16.
hy62sf16804b rev.01/oct. 2002 3 recommended dc operating condition symbol parameter min. typ. max. unit vcc supply voltage 1.65 1.8 2.3 v vss ground 0 0 0 v v ih input high voltage 1.4 vcc+0.3 v v il input low voltage -0.3 (1) - 0.4 v note : 1. vil = -1.5v for pulse width less than 30ns dc electrical characteristics vcc = 1.65v~2.3v, t a = 0 c to 70 c / -40 c to 85 c sym parameter test condition min. typ. max. unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il, / ub = /lb = v ih -1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il, i i/o = 0ma - 3 ma cycle time=min,100% duty, i i/o = 0ma, /cs = v il, v in = v ih or v il - 15 ma icc1 average operating current cycle time = 1us, 100% duty, i i/o = 0ma, /cs < 0.2v, v in <0.2v - - 2 ma i sb ttl standby current (ttl input) /cs = v ih or /ub=/lb= v ih , v in = v ih or v il - - 300 ua sl - - 8 i sb1 standby current (cmos input) /cs > vcc - 0.2v or /ub=/lb > vcc-0.2v, v in > vcc-0.2v or v in < vss+0.2v ll 1 15 ua v ol output low voltage i ol = 0.1ma - - 0.2 v v oh output high voltage i oh = -0.1ma 1.4 - - v note : 1. typical values are at vcc = 1.8v, t a = 25 c 2. typical values are sampled and not 100% tested capacitance (temp = 25 c, f = 1.0mhz) symbol parameter conditio n max. unit c in input capacitance(add, /cs, /we, /ub, /lb, /oe) v in = 0v 8 pf c out output capacitance(i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested
hy62sf16804b rev.01/oct. 2002 4 ac charateristics vcc = 1.65v~2.3v, t a = 0 c to 70 c / -40 c to 85 c -70 -85 -10 # symbol parameter min. max. min. max. min max. read cycle 1 trc read cycle time 70 - 85 - 100 - ns 2 taa address access time - 70 - 85 - 100 ns 3 tacs chip select access time - 70 - 85 - 100 ns 4 toe output enable to output valid - 35 - 40 - 45 ns 5 tba /lb, /ub access time - 70 - 85 - 100 ns 6 tclz chip select to output in low z 10 - 10 - 10 - ns 7 tolz output enable to output in low z 5 - 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - 10 - ns 9 tchz chip deselection to output in high z 0 20 0 30 0 30 ns 10 tohz out disable to output in high z 0 20 0 30 0 30 ns 11 tbhz /lb, /ub disable to output in high z 0 20 0 30 0 30 ns 12 toh output hold from address change 10 - 10 - 15 - ns write cycle 13 twc write cycle time 70 - 85 - 100 - ns 14 tcw chip selection to end of write 60 - 70 - 80 - ns 15 taw address valid to end of write 60 - 70 - 80 - ns 16 tbw /lb, /ub valid to end of write 60 - 70 - 80 - ns 17 tas address set-up time 0 - 0 - 0 - ns 18 twp write pulse width 50 - 60 - 70 - ns 19 twr write recovery time 0 - 0 - 0 - ns 20 twhz write to output in high z 0 20 0 25 0 25 ns 21 tdw data to write time overlap 30 - 35 - 45 - ns 22 tdh data hold from write time 0 - 0 - 0 - ns 23 tow output active from end of write 5 - 5 - 10 - ns ac test conditions t a = 0 c to 70 c / -40 c to 85 c, unless otherwise specified parameter value input pulse level 0.2v to vcc-0.2v input rise and fall time 5ns input and output timing reference level 0.9v tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow cl = 30pf + 1ttl load output load other cl = 30pf + 1ttl load ac test loads d out 3150 ohm cl(1) 3070 ohm v tm = 1.8v note 1. including jig and scope capacitance unit
hy62sf16804b rev.01/oct. 2002 5 timing diagram read cycle 1(note 1,4) read cycle 2(note 1,2,4) trc taa data valid previous data toh toh addr data out read cycle 3(note 1,2,4) /cs /ub, /lb tacs data valid tclz(3) tchz(3) data out notes: 1. a read occurs during the overlap of a low /o e, a high /we, a low /cs and low /ub and /or /lb 2. /oe = v il 3. tchz and tohz are defined as the time at wh ich the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active addr trc /cs taa tacs toh data valid high-z data out /ub ,/ lb /oe tba toe tclz (3) tblz (3) tolz (3) tchz (3) tbhz (3) tohz (3)
hy62sf16804b rev.01/oct. 2002 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 (note 1,4,8) (/cs controlled) data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in high-z tas twhz (3,7) tdw tdh tow (5) (6) data valid addr data out / cs / ub , / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high-z high-z tas
hy62sf16804b rev.01/oct. 2002 7 notes: 1. a write occurs during the overlap of a low / we, a low /cs1 and low /ub and /or /lb 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output st ate so that the input signal s of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simult aneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active data retention electric characteristic t a = 0 c to 70 c / -40 c to 85 c symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v or /ub=/lb > vcc-0.2v, v in > vcc-0.2v or v in < vss+0.2v 1.2 - 2.3 v ll - 1 12 ua i ccdr data retention current vcc=1.5v, /cs > vcc - 0.2v or /ub=/lb > vcc-0.2v, v in > vcc-0.2v or v in < vss+0.2v sl - - 8 ua tcdr chip deselect to data retention time 0 - - ns tr operating recovery time see data retention timing diagram trc (2) - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. trc is read cycle time. data retention timing diagram /cs or /ub & /lb vdr /cs>vcc-0.2v or /ub=/lb > vcc-0.2v tcdr tr vss vcc 1.65v v ih data retention mode
hy62sf16804b rev.01/oct. 2002 8 package information 48ball fine pitch ball grid array package (f) bottom view top view b a a1 corner index area 654321 a a b c d c c1 e f gc1/2 h b1/2 b1 side view 5e1 e2 c e seating plane 4 a r 3 d(diameter) symbol min. typ. max. a - 0.75 - b - 3.75 - b1 5.9 6.0 6.1 c - 5.25 - c1 8.4 8.5 8.6 d 0.3 0.35 0.4 e 0.9 1.0 1.10 e1 - 0.76 - e2 0.20 0.25 0.30 r - - 0.08 note 1. dimensioning and tolerancing per asme y14. 5m-1994. 2. all dimensions are millimeters. 3. dimension ?d? is measured at the maximum solder ball diameter in a plane parallel to datum c. 4. primary datum c(seating plane) is defined by the crown of the solder balls. 5. this is a controlling dimension.
hy62sf16804b rev.01/oct. 2002 9 marking instruction package marking example h y s f 6 0 4 b c s s t y w w p x x x x x k o r fbga index hysf6804b : part name c : power consumption - d : low low power - s : super low power ss : speed - 70 : 70ns - 85 : 85ns t : temperature - c : commercial ( 0 ~ 70 c) - i : industrial ( -40 ~ 85 ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non-fixed item package marking example h y f 6 8 c s s t y w w p x x x x x k o r index ? : part name c : power consumption - d : low low power - s : super low power ss : speed -: - t : temperature - c : commercial ( ) - i : industrial ( - ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non-fixed item ? ? ? ? ? ? ? ? c - 10 : 100ns - package marking example h y s f 6 0 4 b c s s t y w w p x x x x x k o r fbga index hysf6804b : part name c : power consumption - d : low low power - s : super low power ss : speed - 70 : 70ns - 85 : 85ns t : temperature - c : commercial ( 0 ~ 70 c) - i : industrial ( -40 ~ 85 ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non-fixed item package marking example h y f 6 8 c s s t y w w p x x x x x k o r index ? : part name c : power consumption - d : low low power - s : super low power ss : speed -: - t : temperature - c : commercial ( ) - i : industrial ( - ) y : year (ex : 0 = year 2000, 1= year 2001) ww : work week ( ex : 12 = work week 12 ) p : process code xxxxx : lot no. kor : origin country note - capital letter : fixed item - small letter : non-fixed item ? ? ? ? ? ? ? ? c - 10 : 100ns -
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